The present invention relates to electronic timer apparatus, in general, and more particularly to an electronic timer comprising a plurality of modulo counter stages controllable by write signals generated by a central controller and a method for testing the same.
Electronic timers may comprise a string of modulo counter stages responsive to a reference clock signal for counting up or down. Each counter stage counts through its corresponding modulus value before a successive counter stage may be altered in count. Electronic timers have numerous applications in a variety of commercial and industrial products. An example of one type of application is as a real time clock in which the first counter stage has a modulus value of 60 for seconds, the second counter stage has a modulus value of 60 for minutes, the third counter stage has a modulus value of 12 or 24 for hours, and so on.
Electronic timers of the aforementioned type generally include complex additional circuitry to reliably set and test the modulo counter stages thereof. For those electronic timers which are controlled by a central controller, it is a common practice in the industry to write to, as well as read from, the various counter stages over a common data bus. This operation renders the timer even more complex in design.
Some electronic timers, such as real time clocks, for example, are implemented in portable, battery operated devices, such as wristwatches, radio receivers, and pagers, and the like, which coordinate operations through a central controller. Such portable devices generally include battery saving techniques which maintain a lower voltage potential for the counter stages of the real time clock to offer non-volatility thereof at reduced power, while the central controller and processing circuitry may operate at a higher voltage which is cycled off and on at prescribed intervals to conserve power consumption. In this example, all of the data and control lines between the processing circuitry of the central controller and the various counter stages of the real time clock include bidirectional voltage level translation circuits adding further to the complexity in the design of the electronic timer.
Still further, electronic timers, especially for application in portable, battery operated electronic devices, are implemented in an integrated circuit and more particularly on a single substrate with other processing and memory related circuits, the emphasis being in miniaturization and reduced energy consumption thereof. However, as the timer apparatus becomes more and more complex to compensate for the aforementioned features and drawbacks, the area needed on silicon and energy consumption is increased.
The present invention provides for a much simpler electronic timer architecture, one which is controllable by a central controller and operated at a lower voltage level than that of the central controller. The improved timer architecture is relatively small in size, needs no special test logic and thus affords higher operational performance with regard to the setting and testing thereof while consuming less power. More specifically, the improved timer architecture needs no parallel loading in the setting and testing thereof, thus requiring only one-way voltage level translation circuits. These and other benefits will become more evident from the following description of the preferred embodiment taken together with the accompanying drawings.